RISC-16 web interpreter
(Github)
Upload machine code
Processor state
cycle
n/a
pc
n/a
mem[pc]
n/a
speed
n/a
step
play
pause
Registers
r1 (ra)
n/a
r2 (sp)
n/a
r3 (a0)
n/a
r4 (a1)
n/a
r5 (a2)
n/a
r6 (a3)
n/a
r7 (a4)
n/a
Memory
Display